Designed and implemented with the VHDL source cable set-top box program took pla
Developed with the development of a hardware description language. It is 1980, the U.S. Department of Defense VHSIC (High Speed Integrated Circuits) program, and in 1986 and 1987 respectively, the United States Department of Defense and the IEEE industry standard. Used as a standard hardware design language, VHDL description of a very strong capacity to support the system behavioral, register transfer level and gate-level design of three different levels, so that designers will be in TOP-DOWN design process China can easily use the same language. Moreover, VHDL design is a "concept-driven" high-level design, designers need not through the gate-level description of the circuit schematic, but the target functional description of the details as free from the shackles of the circuit, the designer can concentrate on design and concept, so the design work saves time and effort to accelerate the design cycle, and the conversion process easier. VHDL design of the programmable application specific integrated circuit (ASIC) development plays a very important role.
Since Microsoft put forward the "Venus" project, the set-top box will become the main objectives pursued by the information industry is in the mainstream of information appliance products. States are stepping up to the set-top box development, China also made a corresponding "Nu Wa" program, people in many research institutes and manufacturers are doing research in this area. Since our cable is rich in resources, large market potential, and therefore also on the cable TV set-top box of eye-catching. However, because of not fully carry out digital TV services, so the debugging process in the set-top box, to find a suitable signal source is not easy, had to use the computer output by way of standard video stream to achieve. Most computers can EISA bus parallel output data rate can not meet the actual work. Although the EISA bus can be a 16-bit parallel data output, but only for a 8 bit parallel data processing device, the still need a conversion process. This article describes the design of a data format conversion program. The program CPLD with VHDL on a chip to program it from a 16-bit parallel data into 8-bit parallel data conversion, and EISA data output rate increased population doubled to source requirements.
1, VHDL features VHDL is a design-oriented, multi-level area and was universally accepted, standard hardware description language. It mainly has the following characteristics:
To formally abstract representation of the structure and behavior of the circuit, reducing the difficulty of hardware design.
From top to bottom with (Top-Down) to design, support levels and areas of logic design description; it supports the description of three levels: behavioral description, RTL description, gate-level description (logic synthesis).
Early simulation system can be designed to ensure the correctness.
Main design file written in VHDL source code is easy document management.
Independent of hardware description and implementation process.
As VHDL, the industry has been as an IEEE standard, so its language standards, codes, more stringent syntax, easy sharing and reuse. Moreover, VHDL design is complete, flexible method to support a wide range. Most EDA tools to varying degrees in almost all support VHDL language.
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