DDR2 SDRAM
Overview
Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, the DDR2 I/O buffer transfers data both on the rising and falling edge of the clock (a technique called “double pumping”). The key difference between DDR and DDR2 is that for DDR2 the memory cells are clocked at 1 quarter (rather than half) the rate of the bus. This requires a 4 bit deep prefetch queue, but, without changing the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
DDR2’s bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is 2 bits deep for DDR and 8 bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.
Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bus speeds.
Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR’s 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.
According to JEDEC the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).
Specification standards
Chips and modules
For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins and often come identified by an additional S in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth).
Standard name
Memory clock
Cycle time
I/O Bus clock
Data transfers per second
Module name
Peak transfer rate
Timings
DDR2-400
100 MHz
10 ns
200 MHz
400 Million
PC2-3200
3200 MB/s
3-3-3
4-4-4
DDR2-533
133 MHz
7.5 ns
266 MHz
533 Million
PC2-4200
PC2-43001
4266 MB/s
3-3-3
4-4-4
DDR2-667
166 MHz
6 ns
333 MHz
667 Million
PC2-5300
PC2-54001
5333 MB/s
4-4-4
5-5-5
DDR2-800
200 MHz
5 ns
400 MHz
800 Million
PC2-6400
6400 MB/s
4-4-4
5-5-5
6-6-6
DDR2-1066
266 MHz
3.75 ns
533 MHz
1066 Million
PC2-8500
PC2-86001
8533 MB/s
6-6-6
7-7-7
Note: DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (though it is often rounded up or down), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
1 Some manufacturers label their DDR2 modules as PC2-4300 instead of PC2-4200, PC2-5400 instead of PC2-5300 and PC2-8600 instead of PC2-8500. At least one manufacturer has reported this reflects successful testing at a higher-than standard data rate whilst others simply use the alternate rounding as the name, as described above.
In addition to bandwidth and capacity variants, modules can
Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC.
Be “registered”, which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. “unbuffered”) RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
Note: registered and un-buffered SDRAM generally cannot be mixed on the same channel.
Note that the highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (Bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (Bus clock rate) for the best PC-3200 modules.
Debut
DDR2 was introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These modules are mostly manufacturer optimizations of highest-yielding chips, drawing significantly more power than slower-clocked modules, and usually do not offer much, if any, greater real-world performance.
DDR2 started to become competitive with the older DDR standard by the end of 2004, as modules with lower latencies became available.
Backward compatibility
DDR, DDR2 and DDR3 for Desktop PC’s Comparison Graphic
DDR2 DIMMs are not designed to be backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin modules for DDR and DDR2, however the notch on DDR modules is in a slightly different position than that on DDR2 modules.
Higher performance DDR2 DIMMs are compatible with lower performance DDR2 DIMMs; however, the higher performance module runs at the lower module’s frequency. Using lower performing DDR2 memory in a system capable of higher performance results in the bus running at the rate of the lowest performance memory in use; however, in many systems this performance hit can be mitigated to a small extent by setting the timings of the memory to a lower latency setting.
See also
CAS latency (definition of “CAS 5-5-5-15”, for example)
Dual-channel architecture
Fully Buffered DIMM
SO-DIMM
Unbuffered memory
List of device bandwidths
References
^ JEDEC JESD 208 (section 5, tables 15 and 16)
^ DDR2 SDRAM SPECIFICATION. JESD79-2E. JEDEC. April 2008. pp. 78. http://www.jedec.org/download/search/JESD79-2E.pdf. Retrieved 2009-03-14.
^ SPECIALITY DDR2-1066 SDRAM. JEDEC. November 2007. pp. 70. http://www.jedec.org/download/search/JESD208.pdf. Retrieved 2009-03-14.
^ Mushkin PC2-5300 vs. Corsair PC2-5400
^ Ilya Gavrichenkov. “DDR2 vs. DDR: Revenge gained”. X-bit Laboratories. http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html.
Further reading
JEDEC standard: DDR2 SDRAM Specification (JESD79-2F, November 2009)
JEDEC standard: DDR2-1066
“JEDEC Standard No. 21C: 4.20.13 240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification” (PDF). JEDEC Solid State Technology Association. 2008-10. http://www.jedec.org/download/search/4_20_13R18.pdf. Retrieved 2008-12-26.
Razak Mohammed Ali. “DDR2 SDRAM interfaces for next-gen systems” (PDF). Electronic Engineering Times. http://www.eetasia.com/ARTICLES/2006OCT/PDF/EEOL_2006OCT16_INTD_STOR_TA.pdf.
External links
JEDEC website
Overview of DDR-II technology
DDR2 low latency vs high bandwidth, Core 2 Duo (Conroe) performance
v d e
Types of DRAM
Asynchronous
FPM RAM EDO RAM
Synchronous
SDRAM DDR SDRAM Mobile DDR DDR2 SDRAM DDR3 SDRAM
Graphics
VRAM GDDR2 GDDR3 GDDR4 GDDR5
Rambus
RDRAM XDR DRAM XDR2 DRAM
Categories: SDRAM
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