Flip chip
Process steps
Integrated circuits are created on the wafer
Pads are metalized on the surface of the chips
Solder dots are deposited on each of the pads
Chips are cut
Chips are flipped and positioned so that the solder balls are facing the connectors on the external circuitry
Solder balls are then remelted (typically using hot air reflow)
Mounted chip is nderfilled using an electrically-insulating adhesive
Comparison of mounting technologies
Wire bonding/Thermosonic bonding
The interconnections in a power package are made using thick aluminium wires (250 to 400 m) wedge-bonded
In typical semiconductor fabrication systems chips are built up in large numbers on a single large wafer of semiconductor material, typically silicon. The individual chips are patterned with small pads of metal near their edges that serve as the connections to an eventual mechanical carrier. The chips are then cut out of the wafer and attached to their carriers, typically via wire bonding such as Thermosonic Bonding. These wires eventually lead to pins on the outside of the carriers, which are attached to the rest of the circuitry making up the electronic system.
Flip chip
Side-view schematic of a typical flip chip mounting
The processing of a flip chip is similar to conventional IC fabrication with the addition of a few steps. Near the end of the process the attachment pads are metalized to make them more suitable for being soldered onto. This typically consists of several treatments. A small dot of solder is then deposited on each of the pads. The chips are then cut out of the wafer as normal.
Recently high speed mounting methodology evolved through a cooperation between Reel Service Ltd. and Siemens AG in the development of a high speed mounting tape known as ‘MicroTape.’. By adding a tape and reel process into the assembly methodology, placement at high speed, typically 20,000 placements per hour are achievable using standard PCB assembly equipment.[citation needed]
To attach the flip chip into a circuit, it is inverted to bring the solder dots down onto connectors on the underlying electronics or circuit board. The solder is then re-melted to produce an electrical connection, typically using an ultrasonic or alternatively reflow solder process. This also leaves a small space between the chip’s circuitry and the underlying mounting. In most cases an electrically-insulating adhesive is then “underfilled” to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system.
Advantages
The resulting completed flip chip assembly is much smaller than a traditional carrier-based system; the chip sits directly on the circuit board, and is much smaller than the carrier both in area and height. The short wires greatly reduce inductance, allowing higher-speed signals, and also carry heat better.
Disadvantages
Flip chips have several disadvantages. The lack of a carrier means they are not suitable for easy replacement, or manual installation. They also require very flat surfaces to mount to, which is not always easy to arrange, or sometimes difficult to maintain as the boards heat and cool. Also, the short connections are very stiff, so the thermal expansion of the chip must be matched to the supporting board or the connections can crack.
History
The process was originally introduced commercially by IBM in the 1960s for ICs being used in the mainframe systems. DEC followed IBM’s lead but was unable to achieve the quality they demanded, and eventually gave up on the concept. In the 1970s it was taken up by Delco Electronics, and has since become very common in automotive applications.
Alternatives
Since the flip chip’s introduction a number of alternatives to the solder bumps have been introduced, including gold balls or molded studs, electrically conductive polymer and the “plated bump” process that removes an insulating plating by chemical means. Flip chips have recently gained popularity among manufacturers of cell phones, pagers and other small electronics where the size savings are valuable.[citation needed]
See also
Solid Logic Technology
IBM 3081
References
^ Solder Bump Flip Chip
^ Demerjian, Charlie (2008-12-17), Nvidia chips show underfill problems, The Inquirer, http://www.theinquirer.net/inquirer/news/052/1050052/nvidia-chips-show-underfill-problems, retrieved 2009-01-30
^ Introduction to Flip Chip: What, Why, How
Further reading
Wikihowto: Guide to IC packages
hallenges in the Assembly of Large Die, High Bump Density Pb-Free Flip Chip Packages, J. Libres, K. Robinson , Int Electronics Manufacturing Technology Symposium 2007 p. 346
hermal and Mechanical Behaviors of Underfills for Flip-Chip Packaging, H. Wu, C. Poo, L. Waf, and W. Mee, Electronics Packaging Technology Conference 2005 p. 842
lip Chip Processing Using Wafer-Applied Underfills, S. Busch and D. Baldwin [Ga Tech], Electronic Components and Technology Conference 2005 p. 297
he effect of underfill imperfections on the reliability of flip chip modules: FEM simulations and experiments, S. Rzepka, F. feustel, E. Meusel, M. Korhonen and C. Li, 1998 Electronic Components and Technology Conference p. 362
anufacturing Multichip Modules, p. 391ff, by Rakesh Agarwal and Michael Pecht, in Physical Architecture of VLSI Systems, ed. Robert J. Hannemann, Allan D. Kraus and Michael Pecht; John Wiley & Sons Inc., New York (1994)
olderable Contacts for Flip Chip Integrated Circuit Devices, William D. Higdon, Susan Mach, and Ralph Cornell, US Patent 5,547,740, Aug 20, 1996
older jet printing of micropads and vertical interconnects, Wallace, D.B.; Hayes, D.J., SMTA National Symposium, Emerging Technologies. Proceeding of the Technical Program Edina, MN, USA: Surface Mount Technol. Assoc, 1997. p. 55-61 Conference: Bloomington, MN, USA, 20-23 Oct 1997
dvanced solder flip chip processes , Rinne, G.; Koopman, N.; Magill, P.; Nangalia, S.; Berry, C.; Mis, D.; Rogers, V.; Adema, G.; Berry, M.; Deane, P. SMI. Surface Mount International. Advanced Electronics Manufacturing Technologies. Proceedings of The Technical Program Edina, MN, USA: Surface Mount Technol. Assoc, 1996. p. 282-92 vol.1 of 2 vol. 826 pp. Conference: San Jose, CA, USA, 10-12 Sept 1996
older Bump Transfer Device for Flip Chip Integrated Circuit Devices, Shing Yeh, William Higdon, Ralph Cornell, US Patent 5,607,099 Mar 4, 1997
rocess for Converting a Wire Bond Pad to a Flip Chip Solder Bump Pad and Pad Formed Thereby, Curt Erickson, US Patent 5,891,756 April 6, 1999
rocess for Manufacturing a Multilayer Bumped Semiconductor Device, Kamaran Manteghi, US Patent 5,863,812 Jan 26, 1999
ethod of forming solder bumps, Toshiharu Yanagida , US Patent 5,866,475; Feb. 2, 1999
lip-chip packaging for smart MEMS , Mayer, F.; Ofner, G.; Koll, A.; Paul, O.; Baltes, H., Proceedings of the SPIE (1998) vol.3328, p. 183-93. Conference: Smart Structures and Materials 1998: Smart Electronics and MEMS. San Diego, CA, USA, 2-4 March 1998
afer bumping technologies. A comparative analysis of solder deposition processes and assembly considerations, Patterson, D.S.; Elenius, P.; Leal, J.A., Advances in Electronic Packaging 1997. Proceedings of the Pacific Rim/ASME International Intersociety Electronic and Photonic Packaging Conference. INTERpack ASME, 1997. p. 337-51 vol.1Conference: Kohala Coast, HI, USA, 15-19 June 1997
older Flip Chips Employing Electroless Nickel: An Evaluation of Reliability and Cost, F. Stepniak , Advances in Electronic Packaging 1997 p. 353 (EEP Vol 19-1), ASME 1997
incation characterization for electroless Ni/Au UBM of solder bumping technology, Tan, Q.; Beddingfield, C.; Mistry, A.; Mathew, V., Twenty Third IEEE/CPMT International Electronics Manufacturing Technology Symposium,New York, NY, USA: IEEE, 1998. p. 34; Conference: Austin, TX, USA, 19-21 Oct 1998
older bumping methods for flip chip packaging, Rinne, G.A., 1997 Proceedings. 47th Electronic Components and Technology Conference IEEE, 1997. p. 240 Conference: San Jose, CA, USA, 18-21 May 1997
lip-chip packaging with micromachined conductive polymer bumps, Oh, K.W.; Ahn, C.H. , Proceedings of 3rd International Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing 1998, p. 224 Conference: Binghamton, NY, USA, 28-30 Sept 1998
ow cost solder flip chip, Rinne, G.A.; Magill, P.A. , Proceedings. 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces 1997. p. 113 Conference: Braselton, GA, USA, 9-12 March 1997
lip-chip packaging using micromachined conductive polymer bumps and alignment pedestals for MOEMS, Oh, K.W.; Ahn, C.H.; Roenker, K.P., IEEE Journal of Selected Topics in Quantum Electronics (Jan.-Feb. 1999) vol.5, no.1, p. 119
External links
Flip chip assembly videos
Flip chip tutorials
Flip Chip Assembly
Flip Chip (C4) Benefits
Kyocera America, Inc. – White Paper: Flip Chip Challenges
A case for the application of MicroTape
Pushing the barriers of wafer level device integration to higher assembly speed
Flip Chip Packaging Technology Solutions
Molded Flip Chip – FCmBGA White Paper
Categories: Chip carriersHidden categories: All articles with unsourced statements | Articles with unsourced statements from October 2009
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